Asic Dft Engineer | 8+ Years | Dft/atpg/mbist/scan/jtag
Cisco UK
8-10 years asic dft experience
Jtag protocols and scan insertion
Atpg and eda tools like tetramax
The role involves implementing Hardware Design-for-Test features to support ATE, in-system test, and diagnostics for Cisco's core switching and routing products
Job Summary
The role involves implementing Hardware Design-for-Test features to support ATE, in-system test, and diagnostics for Cisco's core switching and routing products.
Candidates will collaborate with multi-functional teams to develop innovative DFT IP and play a key role in full chip design integration.
Cisco offers a global environment where engineers can shape ground-breaking solutions using the unified Silicon One architecture.
Matching Summary
The role involves implementing Hardware Design-for-Test features to support ATE, in-system test, and diagnostics for Cisco's core switching and routing products.
Skills & Requirements
Must-have
8-10 years ASIC DFT experience
Jtag protocols and Scan insertion
ATPG and EDA tools like Tetramax
Gate level simulation with VCS
Post-silicon validation and debug
Tcl Python Perl scripting skills
Nice-to-have
Test Static Timing Analysis
Innovative trends in silicon engineering
Ability to work with minimal mentorship
Strong verbal communication skills
Key Requirements
Bachelor's or Master's Degree in Electrical or Computer Engineering