Sr. Principal Functional Verification Engineer: Applied Ml
Cadence Design Systems Inc.
Belo Horizonte, Minas Gerais, Brazil
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Functional verification methodologies
Formal verification
Uvm verification
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Cadence Design Systems Inc. is seeking a Sr. Principal Functional Verification Engineer with expertise in pre-silicon verification methodologies and a passion for applying machine learning to enhance chip design processes. The role is based in Belo Horizonte, Brazil, and focuses on developing innovative verification strategies within a collaborative and innovative work environment.
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Job Summary
Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
Matching Summary
Match Score: 75
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Cadence Design Systems Inc. is seeking a Sr. Principal Functional Verification Engineer with expertise in pre-silicon verification methodologies and a passion for applying machine learning to enhance chip design processes. The role is based in Belo Horizonte, Brazil, and focuses on developing innovative verification strategies within a collaborative and innovative work environment.
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