Physical Design Timing Engineer (sta)

Broadcom

California, United States
Base: $141,300 - $226,000; bonus/equity: discretio...
Asic sta and timing closure
Cadence or synopsys tools expertise
Multi-mode multi-corner timing analysis
The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions

Job Summary

  • The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions.
  • Broadcom offers a competitive and comprehensive benefits package including medical, dental and vision plans, 401(K) participation with company matching, and an Employee Stock Purchase Program.
  • This position is eligible for a discretionary annual bonus and equity awards in accordance with relevant plan documents.

Matching Summary

The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions.

Salary

Base: $141,300 - $226,000; Bonus/Equity: Discretionary annual bonus and equity awards; Benefits: Medical, dental, vision, 401(K) with matching, ESPP, paid leave

Skills & Requirements

Must-have

  • ASIC STA and timing closure
  • Cadence or Synopsys tools expertise
  • Multi-mode multi-corner timing analysis
  • SDC constraint development
  • Tcl, Python, and Perl scripting
  • On-chip variation and signal integrity knowledge

Nice-to-have

  • Cross-functional collaboration
  • Problem solving skills
  • Clear and precise communication
  • Documenting best practices

Key Requirements

  • Bachelor’s degree in Electrical or Computer Engineering
  • Minimum 12 years ASIC STA experience
  • Experience with timing constraints development
  • Expert proficiency in industry-standard sign-off EDA tools

Work Rights

Not specified

Tailored Resume

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