Design Engineering Architect

BETA CAE Systems International AG

San Jose, US
Base: $178,500 to $331,500; bonus/equity: incentiv...
On-site
Memory interface phy ips
Jedec standards and protocols
Customer-facing technical architect
Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations

Job Summary

  • Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations.
  • Act as a customer-facing technical architect during pre-sales, evaluations, and post-delivery support, clearly articulating architecture choices and trade-offs.
  • Influence product and technology roadmap planning by identifying future standards, protocol evolution, and customer-driven requirements.

Matching Summary

Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations.

Salary

Base: $178,500 to $331,500; Bonus/Equity: Incentive compensation; Benefits: Paid vacation, 401(k), ESPP, medical, dental, vision

Skills & Requirements

Must-have

  • memory interface PHY IPs
  • JEDEC standards and protocols
  • customer-facing technical architect
  • cross-functional collaboration
  • product and technology roadmap planning

Nice-to-have

  • leadership and innovation
  • making an impact on technology

Key Requirements

  • M.S. degree in Electrical Engineering or related field
  • Minimum 15 years of industry experience
  • Strong background in memory interface PHYs
  • Proven ability to own customer-facing technical engagements

Work Rights

Not specified

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