Principal Fpga / Rtl Design Engineer - Signal Processing
Silvus Technologies
Los Angeles, CA, US
$165,000—$250,000 usd py
On-site
Rtl coding, simulation, and test bench development
Fpga synthesis and timing closure
Hardware verification and troubleshooting
The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment
Job Summary
The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment.
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products.
This Principal FPGA / RTL Design Engineer position is based at Silvus headquarters in the heart of vibrant West Los Angeles, CA and is on a hybrid schedule.
Matching Summary
The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment.
Salary
$165,000—$250,000 USD
Skills & Requirements
Must-have
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
Fixed point binary arithmetic and digital signal processing (DSP) designs
Verilog and System-Verilog
Xilinx FPGAs, SoCs, and the Vivado IDE
Nice-to-have
MATLAB skills
Scripting languages such as Perl and Python
Wireless communication systems on FPGA or ASIC designs
Key Requirements
Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
8 years of experience with an advanced degree (MS or PhD)
Must be U.S. Person (U.S. Citizen, or Permanent Resident)
Work Rights
Must be U.S. Person (U.S. Citizen, or Permanent Resident)