Enable next-generation high-speed I/O technologies by leading PHY and SerDes IP validation and integration for future platforms
Job Summary
Enable next-generation high-speed I/O technologies by leading PHY and SerDes IP validation and integration for future platforms.
Lead pre-silicon validation of high-speed I/O PHY IPs for next-generation standards (PCIe Gen7, Ethernet 1.6T, DDR6) and evaluate internal and third-party PHY IPs.
Develop and review PHY integration and architectural guidelines and lead debug and validation of high-speed I/O test chips.
Matching Summary
Enable next-generation high-speed I/O technologies by leading PHY and SerDes IP validation and integration for future platforms.
Skills & Requirements
Must-have
pre-silicon validation
high-speed I/O PHY IPs
SerDes architectures
signal integrity
hardware issues troubleshooting
Nice-to-have
emerging interconnect standards
post-FEC analysis
industry standards engagement
Key Requirements
Bachelor's degree in Electrical Engineering
3+ years of relevant experience
pre-silicon and post-silicon electrical validation