Rtl Design Lead Hardware Engineer

Altera Corporation

Bengaluru, Karnataka, India
Vhdl verilog system verilog expertise
Digital design and timing closure knowledge
Arm based bus protocols understanding
The role involves leading a team of dedicated RTL design engineers to build soft IPs for Altera FPGAs

Job Summary

  • The role involves leading a team of dedicated RTL design engineers to build soft IPs for Altera FPGAs.
  • Responsibilities include developing new interconnect topologies to maximize data transfer throughput over long distances.
  • The engineer will serve as a liaison with support, field, marketing, and product planning organizations to guide IP release content.

Matching Summary

The role involves leading a team of dedicated RTL design engineers to build soft IPs for Altera FPGAs.

Skills & Requirements

Must-have

  • VHDL Verilog System Verilog expertise
  • Digital design and timing closure knowledge
  • ARM based bus protocols understanding
  • Team leadership for RTL engineers
  • AXI APB AHB Avalon protocol experience

Nice-to-have

  • Quartus or Vivado tool flow knowledge
  • Tcl Perl Python scripting skills
  • Customer use case validation experience
  • Streaming protocol IP development
  • Mission critical debug environment support

Key Requirements

  • BS/MS/PhD in Electrical Computer Software Engineering
  • 10+ years of relevant industry experience
  • Strong background in hardware verification fundamentals

Work Rights

Not specified

Tailored Resume

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