Principal Product Validation Engineer

Cadence

Electrical electronics or computer science engineer
Hdls verilog vhdl understanding
Eda tools debugging experience
The role requires an engineer with a strong background in HDLs like Verilog and VHDL for simulation and emulation

Job Summary

  • The role requires an engineer with a strong background in HDLs like Verilog and VHDL for simulation and emulation.
  • Candidates must possess working knowledge of EDA tools to debug design and verification problems effectively.
  • Experience designing complex functional verification environments using SystemVerilog, C++, and UVM is essential.

Matching Summary

The role requires an engineer with a strong background in HDLs like Verilog and VHDL for simulation and emulation.

Skills & Requirements

Must-have

  • Electrical Electronics or Computer Science Engineer
  • HDLs Verilog VHDL understanding
  • EDA tools debugging experience
  • SystemVerilog C++ UVM knowledge
  • Functional Verification of complex digital systems

Nice-to-have

  • Process automation with scripting
  • PCIe USB3/4 DP protocol knowledge
  • SoC Verification experience
  • Complex verification environment design

Key Requirements

  • Electrical, Electronics, or Computer Science Engineering degree
  • Prior experience in simulation/emulation
  • Knowledge of hardware verification languages

Work Rights

Not specified

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