Mixed Signal Logic Verification Engineer

Intel Retiree Medical Plan Trust

Bangalore, India
Hybrid
11-15 years asic/soc verification experience
Expert system verilog and uvm knowledge
Mix signal sensor ip verification expertise
This role requires a Senior or Staff engineer with 11-15 years of experience to drive complex SoC and ASIC verification strategies

Job Summary

  • This role requires a Senior or Staff engineer with 11-15 years of experience to drive complex SoC and ASIC verification strategies.
  • The successful candidate will design advanced test benches using System Verilog and UVM while ensuring coverage closure for mix signal IPs.
  • Candidates must possess expert-level debugging capabilities including RTL debug, gate-level simulations, and formal verification methods.

Matching Summary

This role requires a Senior or Staff engineer with 11-15 years of experience to drive complex SoC and ASIC verification strategies.

Skills & Requirements

Must-have

  • 11-15 years ASIC/SoC verification experience
  • Expert System Verilog and UVM knowledge
  • Mix signal Sensor IP verification expertise
  • Formal verification and model checking skills
  • JTAG/IJTAG/CRI/APB protocol proficiency

Nice-to-have

  • Mentoring junior engineers capability
  • Python Perl Tcl scripting for automation
  • Root Cause Analysis debugging skills
  • Collaboration with architects on top-level verification

Key Requirements

  • 11-15 years of ASIC/SoC verification experience
  • B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI Engineering
  • Hands-on experience with Synopsys VCS, Cadence Xcelium, or Mentor Questa

Work Rights

Not specified

Tailored Resume

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