Astera Labs is seeking a highly skilled Senior/Staff Front-end CAD Engineer to join their newly established R&D center in Israel. The role focuses on developing methodologies, automation scripts, and design flows to enhance chip design processes, particularly for AI applications
Job Summary
Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips.
As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem, architecting methodologies and automation scripts.
Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.
Matching Summary
Match Score: 85
Astera Labs is seeking a highly skilled Senior/Staff Front-end CAD Engineer to join their newly established R&D center in Israel. The role focuses on developing methodologies, automation scripts, and design flows to enhance chip design processes, particularly for AI applications.
Skills & Requirements
Must-have
Python and Tcl scripting
Verilog and/or System Verilog
Linux/Unix environment
EDA tool integration
RTL generation tools
Nice-to-have
VLSI design cycle understanding
Clock domain crossing
Simulation and debugging
Synthesis and timing analysis
Version control systems (Git)
Key Requirements
Bachelor’s degree in Electrical Engineering or related field
5+ years of hands-on professional experience
Proven experience in Python and Tcl
Knowledge and experience in Verilog and/or System Verilog