Principal Engineer, Design Technology Co-optimization

Intel Corporation

Hillsboro, Oregon, US
Base: $220,920.00-311,890.00 usd; bonus/equity: st...
Hybrid
Advanced semiconductor technology understanding
Foundation ip design and dtco
Standard cell library design
The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mmWave circuits and 3D IC, and conducts comprehensive Si validation

Job Summary

  • The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mmWave circuits and 3D IC, and conducts comprehensive Si validation.
  • As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs.
  • We offer a total compensation package that ranks among the best in the industry.

Matching Summary

The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mmWave circuits and 3D IC, and conducts comprehensive Si validation.

Salary

Base: $220,920.00-311,890.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • Advanced semiconductor technology understanding
  • Foundation IP design and DTCO
  • Standard cell library design
  • MOSFET electrical characteristics
  • Library cell characterization and simulation
  • Semiconductor foundry ecosystem experience

Nice-to-have

  • Product design and signoff methodology
  • Pre and post Si foundry benchmarking
  • EDA tool design and optimization
  • Foundation IP Si validation

Key Requirements

  • 10+ years industry experience
  • Ph.D. or Master's degree in EE or CS
  • Excellent oral and written communication
  • Collaborative mindset and team player
  • Technical leadership and delivery track record

Work Rights

Not specified

Tailored Resume

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