Not specified (assumed hybrid or onsite based on typical campus roles)
Dft feature and architecture definition
Good knowledge of digital ic design
Strong knowledge of verilog hdl
NXP Semiconductors is seeking a 2026 Campus - Soc Dft Engineer to participate in DFT feature and architecture definition for complex SOCs. The ideal candidate should possess knowledge in digital IC design and DFT methodologies, including Verilog HDL, and demonstrate a strong commitment to quality and teamwork
Job Summary
Participate in DFT feature and architecture definition for complex SOC.
Implement DFT logic/circuit including SCAN, Boundary SCAN, and MBIST.
Generate DFT related timing constraints and support timing closure.
Matching Summary
Match Score: 75
NXP Semiconductors is seeking a 2026 Campus - Soc Dft Engineer to participate in DFT feature and architecture definition for complex SOCs. The ideal candidate should possess knowledge in digital IC design and DFT methodologies, including Verilog HDL, and demonstrate a strong commitment to quality and teamwork.