Design Verification Engineer

SVENTL ASIA PACIFIC PTE. LTD.

High Street
Sgd 6,000 - 11,500 / monthly pm
On-site
Asic verification and methodologies
System verilog
Sv-ovm/sv-uvm methodologies
Sventl Asia Pacific Pte. Ltd. is seeking a Design Verification Engineer with 3-9 years of experience in ASIC verification. The role involves developing verification environments and test plans, running simulations, and debugging test failures, requiring expertise in System Verilog, RTL concepts, and various communication protocols

Job Summary

  • Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level.
  • Define and develop block/full chip level verification environment and its components.
  • Run simulations and regressions, debug test failures to identify test case and RTL design issues.

Matching Summary

Match Score: 85

Sventl Asia Pacific Pte. Ltd. is seeking a Design Verification Engineer with 3-9 years of experience in ASIC verification. The role involves developing verification environments and test plans, running simulations, and debugging test failures, requiring expertise in System Verilog, RTL concepts, and various communication protocols.

Salary

SGD 6,000 - 11,500 / Monthly

Skills & Requirements

Must-have

  • ASIC Verification and Methodologies
  • System Verilog
  • SV-OVM/SV-UVM Methodologies
  • RTL concepts
  • AHB/AXI protocol
  • PCI-e/USB/Ethernet expertise
  • Perl/TCL scripting

Nice-to-have

  • Good communication skill
  • Experience on MAC, FEC, and Serdes protocols

Key Requirements

  • 3–9+ years ASIC Verification experience

Work Rights

Not specified

Tailored Resume

Cover Letter