Dsp Or Serdes Rtl Sr Principal Digital Design Engineer

Cadence

San Jose, California, United States
Base: $154,000 to $286,000 annually; bonus/equity:...
10+ years serdes experience
Verilog rtl logic design
Digital microarchitecture definition
The role focuses on developing high-speed PMA layer IP for industry-standard protocols within a dynamic team

Job Summary

  • The role focuses on developing high-speed PMA layer IP for industry-standard protocols within a dynamic team.
  • Candidates must possess over a decade of experience in SerDes and a thorough understanding of the end-to-end digital design flow.
  • The position offers competitive compensation including base salary, incentive bonuses, equity, and comprehensive benefits like 401(k) matching.

Matching Summary

The role focuses on developing high-speed PMA layer IP for industry-standard protocols within a dynamic team.

Salary

Base: $154,000 to $286,000 annually; Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k) match, medical/dental/vision

Skills & Requirements

Must-have

  • 10+ years SerDes experience
  • Verilog RTL logic design
  • Digital microarchitecture definition
  • Asynchronous clock domain handling
  • Static timing analysis expertise

Nice-to-have

  • Strong background in DSP algorithms
  • Familiarity with Ethernet PMA/PMD/PCS layers
  • Experience with FPGA and emulation platforms
  • Firmware development of embedded systems
  • Excellent communication and self-motivation

Key Requirements

  • Minimum 10 years of SerDes work experience
  • Substantial Verilog coding skills required
  • Full-time availability at San Jose office

Work Rights

Not specified

Tailored Resume

Cover Letter