Indclutch is seeking a Front End ASIC RTL/Logic Senior Design Engineer to lead the design and implementation of high-speed digital designs in Penang, Malaysia. The ideal candidate should have extensive experience in ASIC frontend design, strong communication skills, and proficiency in RTL coding, among other technical requirements
Job Summary
Responsible to lead, define & implement the design (micro-architecture, RTL, linting, CDC, SDC, UPF/power gating, synthesis) of high speed digital design in next generation IO in cutting edge technology node with multi GigaHz design.
Work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure.
Work on post Silicon debug/characterization support of the designs.
Matching Summary
Match Score: 85
Indclutch is seeking a Front End ASIC RTL/Logic Senior Design Engineer to lead the design and implementation of high-speed digital designs in Penang, Malaysia. The ideal candidate should have extensive experience in ASIC frontend design, strong communication skills, and proficiency in RTL coding, among other technical requirements.
Skills & Requirements
Must-have
High speed digital design
Next generation IO design
Cutting edge technology node
Multi GigaHz design
RTL coding using HDL
Logic simulation and debug environments
Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT
Nice-to-have
Scripting knowledge desirable
Post Silicon debug/characterization support
Key Requirements
Minimum of 10 years of ASIC frontend experience
BS/MS or PhD in Electronics Engineering
Strong communication, leadership, investigation, problem solving & analytical skill