Senior Post Silicon Dft Engineer

Intel Retiree Medical Plan Trust

Haifa, Israel
Hybrid
Post si enabling
Scan and array infrastructure
Dft design
This position is in Intel’s “center of excellence” for Silicon debug supporting Client products

Job Summary

  • This position is in Intel’s “center of excellence” for Silicon debug supporting Client products.
  • This team resolves product quality and performance issues blocking products from meeting production requirements with a combination of design and manufacturing problem solving expertise, leveraging state of the art methodologies & tools.
  • This team is a critical deep portfolio and scaling it going forward.

Matching Summary

This position is in Intel’s “center of excellence” for Silicon debug supporting Client products.

Skills & Requirements

Must-have

  • Post Si enabling
  • Scan and Array infrastructure
  • DFT Design
  • Silicon debug expertise
  • semiconductor circuit design

Nice-to-have

  • Hands-on problem solver
  • state of the art methodologies
  • scaling it going forward
  • Intel's center of excellence

Key Requirements

  • BSC or MSC degree in Engineering
  • Previous experience in semiconductor circuit design
  • Strong verbal and written communication skills (English)
  • Previous experience in Array and Scan infrastructure
  • Design and Post Si enabling

Work Rights

Not specified

Tailored Resume

Cover Letter