Develops the logic design, register transfer level (RTL) coding, and simulation for DDRPHY IP, participating in the definition of architecture and microarchitecture features
Job Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for DDRPHY IP, participating in the definition of architecture and microarchitecture features.
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence, applying strategies to meet power, performance, area, and timing goals.
Follows secure development practices to address security threat models and drives IP handoff quality and compliance.
Matching Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for DDRPHY IP, participating in the definition of architecture and microarchitecture features.