Sr. Ip Logic Design Engineer

Inteelabs

Santa Clara, California, US
$190,610.00-269,100.00 usd; not specified; health,...
Hybrid
Memory coherency protocols
Interconnect topologies
Rtl code in verilog/systemverilog
Inteelabs is seeking a Sr. IP Logic Design Engineer to design scalable memory coherency protocols and interconnect topologies for data center and AI SoCs. The ideal candidate will have over ten years of experience in SoC design, particularly in memory systems and RTL coding, and will benefit from a competitive compensation and hybrid work environment

Job Summary

  • Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
  • Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.
  • We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and comprehensive benefit programs.

Matching Summary

Match Score: 85

Inteelabs is seeking a Sr. IP Logic Design Engineer to design scalable memory coherency protocols and interconnect topologies for data center and AI SoCs. The ideal candidate will have over ten years of experience in SoC design, particularly in memory systems and RTL coding, and will benefit from a competitive compensation and hybrid work environment.

Salary

$190,610.00-269,100.00 USD; Not specified; health, retirement, and vacation

Skills & Requirements

Must-have

  • memory coherency protocols
  • interconnect topologies
  • RTL code in Verilog/SystemVerilog
  • performance modeling and analysis
  • cross-functional collaboration

Nice-to-have

  • AI/ML accelerator design
  • software-hardware co-design
  • workflow automation scripting
  • emerging technologies in memory subsystems

Key Requirements

  • MS/PhD in Electrical Engineering or related field
  • 10+ years in SoC design
  • Expertise in memory coherency protocols
  • Strong knowledge of interconnect technologies
  • Proven RTL coding experience
  • Proficiency in simulation tools
  • Familiarity with physical design implications

Work Rights

Not specified

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