Verification Engineer Intern

Ambarella

Verilog and system verilog programming
Uvm methodology experience
C and c++ coding skills
Ambarella designs complex SoCs including custom DSP and computer vision blocks for edge applications

Job Summary

  • Ambarella designs complex SoCs including custom DSP and computer vision blocks for edge applications.
  • Interns will develop test benches, write random test generators, and create coverage monitors to validate RTL logic.
  • The program requires interns to deliver assignments on time and present their work at the conclusion of the internship.

Matching Summary

Ambarella designs complex SoCs including custom DSP and computer vision blocks for edge applications.

Skills & Requirements

Must-have

  • Verilog and System Verilog programming
  • UVM methodology experience
  • C and C++ coding skills
  • RTL logic debugging capabilities
  • Random test generator development

Nice-to-have

  • Perl or Python scripting proficiency
  • Assembly code familiarity
  • Self-motivated and creative mindset
  • Quick learning ability for new tools
  • Strong interest in computer architecture

Key Requirements

  • Near completion of master's degree
  • Exposure to VLSI design concepts
  • Ability to pick up missing skills quickly

Work Rights

Not specified

Tailored Resume

Cover Letter