Performs functional logic verification of an integrated SoC to ensure design will meet specifications
Job Summary
Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Matching Summary
Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
Skills & Requirements
Must-have
SoC functional logic verification
System Verilog, OVM, UVM
Test Bench bring-up
Verification environment development
Simulation and emulation environments
Nice-to-have
Security activities within test plans
DFD component experience
Collaboration with cross-functional teams
Key Requirements
4 to 9 years of experience
Bachelor's degree in electrical engineering or computer engineering
Master's degree in electrical engineering or computer engineering
3+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content. Monitoring and improve existing simulation environments and simulation efficiency.