Lead Solutions Engineer

Cadence

System verilog experience
Uvm based functional verification environment development
Amba protocols expertise (axi/ahb/apb)
The role involves developing constrained random verification environments and writing tests to meet verification goals for SOC designs

Job Summary

  • The role involves developing constrained random verification environments and writing tests to meet verification goals for SOC designs.
  • Candidates must possess a strong background in functional verification fundamentals, including environment planning and test plan generation.
  • The position requires expertise in AMBA protocols such as AXI, AHB, and APB, along with knowledge of high-speed interfaces like USB or PCIe.

Matching Summary

The role involves developing constrained random verification environments and writing tests to meet verification goals for SOC designs.

Skills & Requirements

Must-have

  • System Verilog experience
  • UVM based functional verification environment development
  • AMBA protocols expertise (AXI/AHB/APB)
  • Constrained random verification environments
  • SOC verification test cases

Nice-to-have

  • Prior Cadence tools and flows experience
  • ARM/CPU architecture familiarity
  • Formal Verification experience
  • Assembly language programming skills
  • Strong communication and presentation skills

Key Requirements

  • Strong background on functional verification fundamentals
  • Experience with UVM based functional verification environment development
  • Good knowledge of verilog/vhdl/C/C++/Perl/Python
  • Expertise in AMBA protocols (AXI/AHB/APB)

Work Rights

Not specified

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