Staff Asic Design Engineer – Ai/ml Hardware Ip Category Location Toronto, Ontario

Talentlab Inc

Toronto, Ontario, Canada
On-site
5+ years asic design experience
Verilog/systemverilog rtl design
Clock domain crossing analysis
This role involves defining micro-architecture and detailed specifications for next-generation AI/ML hardware IP

Job Summary

  • This role involves defining micro-architecture and detailed specifications for next-generation AI/ML hardware IP.
  • The engineer will develop performance-optimized RTL designs focusing on area and power efficiency.
  • Candidates must collaborate with verification teams to define test plans and analyze coverage reports.

Matching Summary

This role involves defining micro-architecture and detailed specifications for next-generation AI/ML hardware IP.

Skills & Requirements

Must-have

  • 5+ years ASIC design experience
  • Verilog/SystemVerilog RTL design
  • Clock domain crossing analysis
  • Power optimization techniques
  • Formal verification with SVA

Nice-to-have

  • AI/ML hardware block experience
  • Python scripting proficiency
  • Cross-functional collaboration skills
  • AXI bus protocol knowledge

Key Requirements

  • Bachelor's degree in Electrical Engineering
  • Legally authorized to work in Canada
  • Proficiency in synthesis and timing tools

Work Rights

Must be legally authorized to work on-site in Canada

Tailored Resume

Cover Letter