Principal Asic Design Engineer

Marvell Technology

Base: 145,800 - 194,400 cad; bonus/equity: not spe...
Not specified
Verilog/system verilog rtl coding
Experience with asic design flow
Micro-architecture and rtl development
Marvell Technology is seeking a Principal ASIC Design Engineer to join its team, focusing on the development of advanced SoCs for their CXL product roadmap. The ideal candidate will have a strong background in ASIC design, micro-architecture, and RTL development, along with a collaborative approach to working with cross-functional teams

Job Summary

  • Marvell’s semiconductor solutions are essential for data infrastructure.
  • As a Principal Design Engineer, you will lead micro-architecture and RTL development.
  • The role offers competitive compensation and a collaborative work environment.

Matching Summary

Match Score: 85

Marvell Technology is seeking a Principal ASIC Design Engineer to join its team, focusing on the development of advanced SoCs for their CXL product roadmap. The ideal candidate will have a strong background in ASIC design, micro-architecture, and RTL development, along with a collaborative approach to working with cross-functional teams.

Salary

Base: 145,800 - 194,400 CAD; Bonus/Equity: Not specified; Benefits: Not specified

Skills & Requirements

Must-have

  • Verilog/System Verilog RTL coding
  • Experience with ASIC design flow
  • Micro-architecture and RTL development

Nice-to-have

  • Mentorship of junior team members
  • Scripting in Perl/Python/Shell
  • Expertise in Computer Architecture

Key Requirements

  • Bachelor’s degree in related fields
  • 12+ years of professional experience
  • Master’s degree or PhD with 10+ years of experience

Work Rights

Not specified

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