Synthesis & Front-end Implementation Engineer

NXP USA INC.

Pune, India
On-site
Rtl synthesis
Timing constraints (sdc)
Sta and timing closure
NXP USA INC. is seeking a Synthesis & Front-End Implementation Engineer in Pune, India, to play a vital role in converting RTL designs into optimized gate-level netlists. The ideal candidate will have a strong background in digital ASIC/SoC design, with expertise in synthesis, timing analysis, and verification

Job Summary

  • Perform synthesis of RTL designs for various digital blocks and sub-systems, including hierarchical synthesis methodologies.
  • Conduct STA, identify critical paths, and collaborate with design teams for timing closure.
  • Develop and maintain automation scripts (Tcl, Python, Perl) for synthesis flows and design analysis.

Matching Summary

Match Score: 85

NXP USA INC. is seeking a Synthesis & Front-End Implementation Engineer in Pune, India, to play a vital role in converting RTL designs into optimized gate-level netlists. The ideal candidate will have a strong background in digital ASIC/SoC design, with expertise in synthesis, timing analysis, and verification.

Skills & Requirements

Must-have

  • RTL synthesis
  • timing constraints (SDC)
  • STA and timing closure
  • formal verification (LEC)
  • power analysis
  • area optimization
  • automation scripting (Tcl, Python, Perl)

Nice-to-have

  • collaboration with design teams
  • evaluation of new CAD tools
  • knowledge of DFT principles

Key Requirements

  • 2+ years of experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • Proficiency with industry-standard synthesis tools
  • Strong understanding of static timing analysis (STA) concepts
  • Experience with formal verification tools
  • Understanding of UPF, low-power design techniques
  • Solid knowledge of Verilog/System Verilog

Work Rights

Not specified

Tailored Resume

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