Lead Solutions Engineer

Cadence

San Jose, California, US
Base: $114,800 to $213,200; bonus/equity: eligible...
Vlsi design experience
Physical verification domain expertise
Ic design flow understanding
The role focuses on validating and optimizing advanced physical verification technologies for cutting-edge semiconductor designs

Job Summary

  • The role focuses on validating and optimizing advanced physical verification technologies for cutting-edge semiconductor designs.
  • Engineers will collaborate closely with design teams, product engineering, and R&D to ensure solutions meet stringent production requirements.
  • Candidates must demonstrate strong aptitude for out-of-the-box thinking and problem-solving in complex hierarchical design environments.

Matching Summary

The role focuses on validating and optimizing advanced physical verification technologies for cutting-edge semiconductor designs.

Salary

Base: $114,800 to $213,200; Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, holidays, 401(k) match, stock purchase plan

Skills & Requirements

Must-have

  • VLSI design experience
  • Physical verification domain expertise
  • IC Design Flow understanding

Nice-to-have

  • Programming background
  • Fast learner aptitude
  • Out-of-the-box problem solving

Key Requirements

  • Work experience in VLSI design
  • Strong understanding of semiconductor manufacturing
  • Knowledge of device physics and modeling

Work Rights

Not specified

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