Sr Principal Application Engineer - Emulation

Cadence

6+ years hdl design and verification experience
Experience with eda tools simulators and debuggers
Proficiency in systemverilog uvm or systemc
The role involves providing technical pre-sales and post-sales services for Cadence's functional verification products

Job Summary

  • The role involves providing technical pre-sales and post-sales services for Cadence's functional verification products.
  • Candidates must possess at least six years of experience in HDL design and verification using languages like SystemVerilog.
  • The position requires strong programming skills in scripting languages such as Python, C++, and Perl to efficiently perform tasks.

Matching Summary

The role involves providing technical pre-sales and post-sales services for Cadence's functional verification products.

Skills & Requirements

Must-have

  • 6+ years HDL design and verification experience
  • Experience with EDA tools simulators and debuggers
  • Proficiency in SystemVerilog UVM or SystemC
  • Programming skills in Python C++ Perl Tcl
  • Fluency in Japanese and English technical communication

Nice-to-have

  • Hardware emulator or FPGA product development experience
  • Mixed-signal verification experience
  • Experience evaluating EDA tools
  • Ability to build trust with customers
  • Proactive problem-solving and independent work style

Key Requirements

  • Bachelor's degree in Computer Science or Electrical Engineering
  • Minimum 6 years of relevant industry experience
  • Bilingual proficiency in Japanese and English

Work Rights

Not specified

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