Sta Lead Engineer

Samsung Semiconductor India Research (SSIR)

Bangalore, India
Asic development
Timing closure
Low power optimization
Oversee and mentor a team of STA engineers, ensuring timely project execution for a Chip and Subsystems

Job Summary

  • Oversee and mentor a team of STA engineers, ensuring timely project execution for a Chip and Subsystems.
  • Work closely with RTL designer, physical design, low power teams to optimize performance, area and power.
  • Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples.

Matching Summary

Oversee and mentor a team of STA engineers, ensuring timely project execution for a Chip and Subsystems.

Skills & Requirements

Must-have

  • ASIC development
  • timing closure
  • low power optimization
  • Perl/Tcl scripting
  • Deep Sub Micron topics

Nice-to-have

  • leading by example
  • improving process efficiency
  • cross-functional team collaboration

Key Requirements

  • 12+ years relevant experience
  • BSEE or MSEE in EE
  • Experience leading Hard-IP/HardBlocks/SOC timing closure
  • Good experience with functional and test mode constraints
  • Experience with low power management implications

Work Rights

Not specified

Tailored Resume

Cover Letter