Asic Design Engineer

Nvidia Corporation

CA, United States
Base: 116,000 usd - 189,750 usd (level 2), 136,000...
On-site
Rtl design verilog
Microarchitecture development
Front-end flows
Drafting microarchitecture documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets and specifications

Job Summary

  • Drafting microarchitecture documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets and specifications.
  • Collaborating closely with architects, other designers, and pre and post silicon verification teams to deliver world-class RTL builds.
  • Assisting the silicon bring-up team in debugging and post-silicon validation activities.

Matching Summary

Drafting microarchitecture documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets and specifications.

Salary

Base: 116,000 USD - 189,750 USD (Level 2), 136,000 USD - 218,500 USD (Level 3); Bonus/Equity: Equity eligible; Benefits: Eligible for benefits

Skills & Requirements

Must-have

  • RTL design Verilog
  • Microarchitecture development
  • Front-end flows
  • Logic synthesis
  • Power and timing analysis
  • Scripting languages Perl, Python

Nice-to-have

  • C/C++ skills
  • Multi clock domains
  • Asynchronous logic
  • Interface protocols
  • Arbitration schemes
  • Problem-solving abilities

Key Requirements

  • BS/MS Degree or equivalent experience
  • 2+ years of relevant RTL design work experience
  • Exposure to Digital systems and VLSI design
  • Exposure to Computer Architecture
  • Exposure to Computer Arithmetic

Work Rights

Not specified

Tailored Resume

Cover Letter