Sophisticated blocks, clusters and top level verification
You will contribute to developing Cisco’s progressive data center by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications
Job Summary
You will contribute to developing Cisco’s progressive data center by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications.
Architect block, cluster and top-level DV environment infrastructure and develop DV infrastructure from scratch.
Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance.
Matching Summary
You will contribute to developing Cisco’s progressive data center by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications.
Skills & Requirements
Must-have
UVM/System Verilog
build test benches from scratch
sophisticated blocks, clusters and top level verification
Nice-to-have
scripting with Perl and/or Python
data path verification
formal verification knowledge
experience with PCIe, Ethernet, RDMA, TCP
Key Requirements
7+ years of related ASIC design verification experience
Bachelor’s Degree or equivalent experience in EE, CE, or other related field