Senior Applications Engineer – Ddr Design Ip

Cadence

San Jose, CA, US
Base: $84,000 to $156,000; bonus/equity: eligible ...
Bs/ms in ee or ce degree
Knowledge of verilog hdl
Experience with simulation tools
The role involves supporting the technical presales of DDR IP by generating collateral through simulations, synthesis, and publications

Job Summary

  • The role involves supporting the technical presales of DDR IP by generating collateral through simulations, synthesis, and publications.
  • Candidates will work closely with IP Sales staff, marketing, and R&D teams to win opportunities and present IP demos to customers.
  • The position offers a competitive salary range of $84,000 to $156,000 along with benefits including a 401(k) plan and employee stock purchase plan.

Matching Summary

The role involves supporting the technical presales of DDR IP by generating collateral through simulations, synthesis, and publications.

Salary

Base: $84,000 to $156,000; Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k), medical, dental, vision

Skills & Requirements

Must-have

  • BS/MS in EE or CE degree
  • Knowledge of Verilog HDL
  • Experience with simulation tools
  • Experience with synthesis tools
  • Excellent presentation skills

Nice-to-have

  • Familiarity with DDR4/5 protocols
  • Perl or Python scripting skills
  • Strong knowledge of ASIC flow
  • Experience with AXI and DFI protocols
  • Collaborative and creative mindset

Key Requirements

  • BS/MS in Electrical Engineering or Computer Engineering
  • Knowledge of Computer Architecture and Electronics circuits
  • Experience with RTL design and verification

Work Rights

Not specified

Tailored Resume

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