Physical Design Subsystem (multiple Ip’s/partitions) Lead

Astera Labs

Israel
**
Physical design subsystem
Rtl to gds execution
Ppa targets
** Astera Labs is seeking a Physical Design Subsystem Lead to join their new R&D center in Israel, focusing on the development of semiconductor chips for AI applications. The role involves overseeing physical design execution, team management, and collaboration across various engineering functions to meet performance targets. **

Job Summary

  • Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve critical 'data bottlenecks' enabling the future of AI at scale.
  • As the Physical Design Subsystem (Multiple IP’s/Partitions) Lead, you will be a Key member of our PD Team in Israel R&D center, running PD execution of Subsystem with your team for chips that drive the world’s largest AI clusters.
  • You will take full ownership of Subsystem physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff.

Matching Summary

Match Score: 75

** Astera Labs is seeking a Physical Design Subsystem Lead to join their new R&D center in Israel, focusing on the development of semiconductor chips for AI applications. The role involves overseeing physical design execution, team management, and collaboration across various engineering functions to meet performance targets. **

Skills & Requirements

Must-have

  • Physical Design Subsystem
  • RTL to GDS execution
  • PPA targets
  • Floorplanning, P&R, CTS
  • Signal integrity, thermal, power challenges
  • Advanced process technologies (5nm, 3nm, and below)

Nice-to-have

  • Building and mentoring teams
  • Collaborating with cross-functional teams
  • Leading external contractors

Key Requirements

  • B.Sc. or M.Sc. in Electrical Engineering
  • 15+ years of hands-on experience in Physical Design/Backend
  • Proven experience in leading teams or projects
  • Deep expertise in RTL2GDS flows
  • Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
  • Experience managing complex Macro-level designs subsystem level and Full-Chip integration

Work Rights

Not specified

Tailored Resume

Cover Letter