Asic Dv Engineer (tcp02 )

HPE

Kolkata, India
Onsite
Asic verification using systemverilog
Uvm verification methodology
Front-end simulator tools (vcs/nc)
You will architect and develop block level verification environments for sub-system and full chip using SystemVerilog and UVM methodology

Job Summary

  • You will architect and develop block level verification environments for sub-system and full chip using SystemVerilog and UVM methodology.
  • HPE offers comprehensive benefits supporting physical, financial, and emotional wellbeing along with personal and professional development programs.
  • HPE fosters an unconditionally inclusive culture that values varied backgrounds and flexibility in managing work and personal needs.

Matching Summary

You will architect and develop block level verification environments for sub-system and full chip using SystemVerilog and UVM methodology.

Skills & Requirements

Must-have

  • ASIC Verification using SystemVerilog
  • UVM verification methodology
  • Front-end simulator tools (VCS/NC)
  • Verification of large ASIC blocks
  • Perl/Python/Shell scripting

Nice-to-have

  • Experience with Ethernet protocols
  • Strong problem solving skills
  • Agile Scrum Development
  • Cross-Functional Teamwork
  • Growth Mindset

Key Requirements

  • MSEE or BSEE degree
  • 3+ years ASIC verification experience
  • Experience in constrained-random verification
  • Experience with OVM/VMM/UVM methodologies
  • Work primarily onsite at HPE office

Work Rights

Not specified

Tailored Resume

Cover Letter