Sr/ IC Design Engineer (Design Verification)

ETHOS TECH ONE PTE. LTD.

Singapore
Systemverilog uvm verification experience
Test plan development and review
Constrained-random verification environment
The role involves developing and reviewing test plans based on IC design specifications for complex DUTs

Job Summary

  • The role involves developing and reviewing test plans based on IC design specifications for complex DUTs.
  • Candidates will create constrained-random verification environments using SystemVerilog and UVM to ensure product performance.
  • Responsibilities include implementing coverage matrices, debugging tests, and resolving bugs with remote designers.

Matching Summary

Match Score: 85

The role involves developing and reviewing test plans based on IC design specifications for complex DUTs.

Skills & Requirements

Must-have

  • SystemVerilog UVM verification experience
  • Test plan development and review
  • Constrained-random verification environment
  • Coverage matrix implementation
  • HDL understanding Verilog VHDL

Nice-to-have

  • Strong analytical and communication skills
  • Remote debugging capabilities
  • Pre-Silicon IP/SOC experience

Key Requirements

  • Bachelor or Masters degree in Engineering
  • Minimum 1 year of verification experience
  • Hands-on Silicon/ IP verification experience

Work Rights

Not specified

Tailored Resume

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