Senior Soc Physical Design/power Analysis/rdl Engineer

Altera

San Jose, California, United States
$127,400 - $184,400 usd; not specified; not specif...
Physical design implementation
Power integrity analysis
Bump/rdl/mimcap planning
Altera provides leadership programmable solutions across the cloud to the edge, enabling limitless possibilities for AI

Job Summary

  • Altera provides leadership programmable solutions across the cloud to the edge, enabling limitless possibilities for AI.
  • Responsibilities include performing Physical Design Implementation and Power Integrity Static and Dynamic Analysis for SoC block and subsystem levels.
  • The role requires conducting all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, and verification and signoff.

Matching Summary

Altera provides leadership programmable solutions across the cloud to the edge, enabling limitless possibilities for AI.

Salary

$127,400 - $184,400 USD; Not specified; Not specified

Skills & Requirements

Must-have

  • Physical Design Implementation
  • Power Integrity Analysis
  • BUMP/RDL/MIMCAP planning
  • Static Timing Analysis
  • Formal Equivalence Verification
  • Scripting languages (Perl, TCL, Python)

Nice-to-have

  • Mentoring junior team members
  • Strong initiative and analytical skills
  • Ability to multitask
  • Low power design methodologies

Key Requirements

  • Bachelor's degree in computer engineering, electronic Engineering or related field
  • 5+ years of relevant experience
  • Multiple tape-out experience in deep submicron process nodes
  • Extensive knowledge of physical design flow and EDA tools
  • Extensive knowledge of physical design signoff flow (STA, LEC, ERC, DRC)
  • Hardware description languages (VHDL, Verilog)

Work Rights

Not specified

Tailored Resume

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