Applied Ml – Functional Verification Engineer

Cadence Design Systems Inc.

San Jose, California, US
Base: $114,800 to $213,200; bonus/equity: incentiv...
Formal verification
Simulation/uvm verification
Debugging pre-silicon failures
You will be part of the ChipStack AI Super Agent team, operating at the forefront of semiconductor design and AI innovation

Job Summary

  • You will be part of the ChipStack AI Super Agent team, operating at the forefront of semiconductor design and AI innovation.
  • Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success.

Matching Summary

You will be part of the ChipStack AI Super Agent team, operating at the forefront of semiconductor design and AI innovation.

Salary

Base: $114,800 to $213,200; Bonus/Equity: Incentive compensation (bonus, equity); Benefits: Paid vacation, 401(k) with match, ESPP, medical, dental, vision

Skills & Requirements

Must-have

  • Formal verification
  • Simulation/UVM verification
  • Debugging pre-silicon failures
  • Verilog, System Verilog, Python
  • AI enhanced EDA tools
  • Agentic AI solutions

Nice-to-have

  • LLMs and ML technologies
  • Customer requirement understanding
  • Continuous learning and innovation
  • Team-oriented environment

Key Requirements

  • Minimum 4 years of experience (BS) or 2 years (MS) or new PhD
  • 3+ years in Formal, SV/UVM, or OVM
  • Experience with Jasper, Xcelium, IMC
  • Excellent communication skills
  • Self-motivated approach

Work Rights

Not specified

Tailored Resume

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