Asic Design Verification Engineer I Intern - United States

Cisco UK

Maynard, United States
Base: $44,000.00 - $185,000.00; bonus/equity: not ...
Systemverilog /uvm
Object-oriented verification methodologies
Verification test benches
The ASIC Design Verification Intern Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products

Job Summary

  • The ASIC Design Verification Intern Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products.
  • This role is focused on verifying highly-complex ASICs that are used in these next-generation telecom systems.
  • We work as a team, collaborating with empathy to make really big things happen on a global scale.

Matching Summary

The ASIC Design Verification Intern Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products.

Salary

Base: $44,000.00 - $185,000.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision insurance, 401(k) plan with matching contribution, paid parental leave, disability coverage, life insurance, restricted stock units, paid time away programs

Skills & Requirements

Must-have

  • SystemVerilog /UVM
  • object-oriented verification methodologies
  • verification test benches
  • test plans execution
  • design verification coding

Nice-to-have

  • fast-learning, self-motivated
  • collaborative and passionate
  • process improvements
  • latest technologies & processes

Key Requirements

  • Currently enrolled in a full-time undergraduate program
  • Knowledge of SystemVerilog /UVM
  • Knowledge of C and/or C++

Work Rights

Not specified

Tailored Resume

Cover Letter