Asic Design Verification Engineer | Uvm | Exp- 8+ Years
Cisco UK
Bangalore, India
Uvm/system verilog
Asic verification
Dv environment infrastructure
You will contribute to developing Cisco’s progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security
Job Summary
You will contribute to developing Cisco’s progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security.
Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.
Matching Summary
You will contribute to developing Cisco’s progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security.
Skills & Requirements
Must-have
UVM/System Verilog
ASIC verification
DV environment infrastructure
constraint random stimulus
code and functional coverage
Gate Level Simulations
Nice-to-have
Forwarding logic/Parsers/P4
Formal verification
emulation support
AI era solutions
Key Requirements
8+ years ASIC design verification experience
Bachelor’s or Master’s Degree in EE, CE, or related field