As part of the ASIC team, you will be developing the ASICs at the heart of each of these switch products
Job Summary
As part of the ASIC team, you will be developing the ASICs at the heart of each of these switch products.
You will have a Design Verification background, hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of C++, scripting, as well as ASIC design and verification flow.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.
Matching Summary
As part of the ASIC team, you will be developing the ASICs at the heart of each of these switch products.
Skills & Requirements
Must-have
System Verilog and UVM methodology
ASIC design and verification flow
block level test benches
end-to-end verification
developing test plans
cross-block verification
Nice-to-have
collaboration with empathy
foster professional growth
cutting-edge technologies
AI era solutions
Key Requirements
at least 8 years of experience
Completed degree in Electrical or Computer engineering