As a Hardware Engineer, you will lead a team of dedicated RTL design Engineers to build soft IPs for Altera FPGAs, coming up with newer versions of on-chip transfer protocols aimed for high speed
Job Summary
As a Hardware Engineer, you will lead a team of dedicated RTL design Engineers to build soft IPs for Altera FPGAs, coming up with newer versions of on-chip transfer protocols aimed for high speed.
The team is responsible for development of RTL for various soft IPs, including an on-chip Memory Mapped Interconnect, streaming protocols IPs, and debug IP such as signaltap.
You will work closely with developers across software, IP and embedded engineering to ensure design flows meet customer needs and guide IP release content.
Matching Summary
As a Hardware Engineer, you will lead a team of dedicated RTL design Engineers to build soft IPs for Altera FPGAs, coming up with newer versions of on-chip transfer protocols aimed for high speed.
Skills & Requirements
Must-have
RTL design
VHDL/Verilog/System Verilog
digital design
on-chip Memory Mapped Interconnect
streaming protocols IPs
debug IP development
Nice-to-have
customer experience and usability
influence across organization boundaries
Computer Architecture
ARM Based Bus Protocols
communication protocols
Key Requirements
10+ years of relevant industry experience
BS/MS/PhD degree in Electrical/Computer/Software Engineering or equivalent
Strong understanding of digital design/Timing Closure/Verification/Hardware Debug
Strong experience in Verilog and System Verilog
Understanding of Computer Architecture/ARM Based Bus Protocols