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Cadence is seeking a Principal Software Engineer for their Verification IP Development team in Ahmedabad, India. The ideal candidate should have extensive experience in functional verification, particularly with SystemVerilog/Universal Verification Methodology (SV/UVM), and possess strong communication skills to collaborate effectively with teams and customers.
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Job Summary
Responsible for the design and development of VIP using C/C++.
Involve in managing multiple VIPs, leading a small team and interacting with customers.
The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
Matching Summary
Match Score: 75
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Cadence is seeking a Principal Software Engineer for their Verification IP Development team in Ahmedabad, India. The ideal candidate should have extensive experience in functional verification, particularly with SystemVerilog/Universal Verification Methodology (SV/UVM), and possess strong communication skills to collaborate effectively with teams and customers.
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