Analog Circuit Design Engineer

Altera

San Jose, California, United States
Base: $127,400 - $180,400 usd; bonus/equity: incen...
Analog circuit design
Mixed-signal circuit design
High-speed io circuits
Design various mixed-signal circuit designs on Altera FPGAs such as voltage regulators, bandgaps and bias circuits, Analog to digital converter (ADC), Delay locked loops (DLLs), high speed clock distribution and other clocking circuits, IO circuits such as high voltage IO, RCOMP/SCOMP, memory circuits etc. on advanced processes nodes

Job Summary

  • Design various mixed-signal circuit designs on Altera FPGAs such as voltage regulators, bandgaps and bias circuits, Analog to digital converter (ADC), Delay locked loops (DLLs), high speed clock distribution and other clocking circuits, IO circuits such as high voltage IO, RCOMP/SCOMP, memory circuits etc. on advanced processes nodes.
  • Deliver all aspects of the design and collateral, including timing and reliability collateral, and drive transitions to AI tool-based design.
  • Collaborate with logic designer, logic verification designer, structural physical design engineers, integration engineers, signal integrity and power deliver engineer to define clear collateral handoff requirements to ensure efficient IP integration.

Matching Summary

Design various mixed-signal circuit designs on Altera FPGAs such as voltage regulators, bandgaps and bias circuits, Analog to digital converter (ADC), Delay locked loops (DLLs), high speed clock distribution and other clocking circuits, IO circuits such as high voltage IO, RCOMP/SCOMP, memory circuits etc. on advanced processes nodes.

Salary

Base: $127,400 - $180,400 USD; Bonus/Equity: Incentive opportunities; Benefits: Not specified

Skills & Requirements

Must-have

  • Analog circuit design
  • Mixed-signal circuit design
  • High-speed IO circuits
  • Clocking circuits
  • Circuit design tools (Virtuoso, Spice, StarRC, Totem)
  • Design for process variation and reliability

Nice-to-have

  • AI tool-based design transition
  • Cross-functional team collaboration
  • Cross-geo team collaboration
  • Motivated team-player
  • Independent self-starter

Key Requirements

  • 4+ years of experience in analog/mixed signal, high speed, or high voltage IO designs
  • BSEE/MSEE/PhD in Electrical Engineering or equivalent
  • Verilog, static timing analysis, UPF understanding

Work Rights

Eligible for U.S. export authorizations

Tailored Resume

Cover Letter