Silicon Packaging Design Engineer

Intel

Phoenix, Arizona, US
Base: $91,150.00-128,690.00 usd; bonus/equity: sto...
Mask and panel design
Physical layout and routing
Substrate design/layout
As an integral part of Intel's new Integrated Device Manufacturer 2.0 (IDM2.0) strategy, we are establishing Foundry Services (FS), a fully vertical, stand-alone foundry business, reporting directly to the CEO

Job Summary

  • As an integral part of Intel's new Integrated Device Manufacturer 2.0 (IDM2.0) strategy, we are establishing Foundry Services (FS), a fully vertical, stand-alone foundry business, reporting directly to the CEO.
  • Silicon packaging engineering responsibilities include driving end-to-end development for mask and panel design from concept through tape out for a given package to produce within the substrate factory.
  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

As an integral part of Intel's new Integrated Device Manufacturer 2.0 (IDM2.0) strategy, we are establishing Foundry Services (FS), a fully vertical, stand-alone foundry business, reporting directly to the CEO.

Salary

Base: $91,150.00-128,690.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • Mask and panel design
  • Physical layout and routing
  • Substrate design/layout
  • DRC analysis and resolution
  • Product lifecycle management

Nice-to-have

  • Creative problem-solving
  • Microelectronics package substrate technology
  • Python, VB, C scripting

Key Requirements

  • Bachelor’s degree in electrical engineering
  • 6+ months relevant experience
  • Valor, Cadence APD, Siemens Xpedition, or CAD software
  • Physical layout aspects of substrate design
  • On-site presence required

Work Rights

Not specified

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