Deep understanding of ddr4/ddr5 and lpddr standards
Experience with high-speed interface validation methodologies
This role involves defining the architecture for next-generation high-speed external memory and general-purpose IO subsystems across Altera's FPGA product portfolio
Job Summary
This role involves defining the architecture for next-generation high-speed external memory and general-purpose IO subsystems across Altera's FPGA product portfolio.
The successful candidate will drive architectural trade-off analysis across performance, power, area, cost, scalability, and reliability while collaborating with cross-functional teams.
Candidates must possess deep expertise in silicon architecture, signal integrity, and timing closure to lead technical reviews and ensure architectural intent is realized in silicon.
Matching Summary
This role involves defining the architecture for next-generation high-speed external memory and general-purpose IO subsystems across Altera's FPGA product portfolio.
Salary
Base: $200,400 - $286,000 USD; Bonus/Equity: Incentive opportunities based on performance; Benefits: Not specified
Skills & Requirements
Must-have
10+ years RTL and ASIC design experience
Deep understanding of DDR4/DDR5 and LPDDR standards
Experience with high-speed interface validation methodologies
Nice-to-have
Knowledge of MIPI, LVDS, and ONFI standards
Experience with advanced packaging technologies
Familiarity with multi-die integration strategies
Key Requirements
Bachelor's Degree in Electrical Engineering
10+ years hands-on experience in RTL and ASIC flows