The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable
Job Summary
The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable.
You will be part of a new verification team which collaborates on the verification of gate-driver ICs and embedded SoCs based on innovative new core architectures.
Join Allegro and become part of a team where your contributions truly matter, fostering a culture of Real Innovation and Real Connection.
Matching Summary
The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable.
Skills & Requirements
Must-have
SystemVerilog and UVM verification
Mixed-signal testbench development
Functional coverage analysis
Constrained random verification methodologies
Bus-functional model development
Debugging unexpected design behavior
Nice-to-have
Collaboration with system engineering teams
Tracking project deliverables and quality focus
Experience with real-numbered analog behavioral models
Script generation for regression control
Key Requirements
Bachelor's degree in Electrical or Electronic Engineering
Knowledge of embedded SoC design and verification lifecycle
Experience with CPU, Memory or I/O Subsystem microarchitectures
Proficiency in SystemVerilog, Verilog, UVM/OVM, Specman, C/C++, ASM, TCL/TK, Python