Senior Design Verification Engineer

Altera

San Jose, California, United States
Base: $142.6k - $206.5k usd; bonus/equity: incenti...
Verilog system verilog uvm development
Ethernet pcie cxl protocol verification
Complex coverage driven random constraint environments
The role involves leading the verification and validation of next-generation IP across Altera's FPGA product portfolios

Job Summary

  • The role involves leading the verification and validation of next-generation IP across Altera's FPGA product portfolios.
  • Candidates must develop comprehensive test plans, create directed and random test cases, and achieve high coverage metrics.
  • The position requires working with cross-functional teams to support IP functional validation tests on actual FPGA development kits.

Matching Summary

The role involves leading the verification and validation of next-generation IP across Altera's FPGA product portfolios.

Salary

Base: $142.6k - $206.5k USD; Bonus/Equity: Incentive opportunities available; Benefits: Not specified

Skills & Requirements

Must-have

  • Verilog System Verilog UVM development
  • Ethernet PCIe CXL protocol verification
  • Complex coverage driven random constraint environments
  • RTL design debugging and isolation
  • FPGA hardware bring-up and validation

Nice-to-have

  • Advanced verification tool development
  • Cross-functional team collaboration
  • System level validation strategy creation

Key Requirements

  • BS/MS in Electrical or Computer Engineering
  • 9+ years industry experience in verification
  • 7+ years Ethernet/PCIe/CXL protocol verification
  • 7+ years UVM fluency and complex environments
  • Eligible for US export authorizations

Work Rights

Must be eligible for US export authorizations

Tailored Resume

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