Mixed Signal Logic Design Engineer

Intel Corporation

Penang, Malaysia
Hybrid
8+ years of rtl coding experience
Systemverilog implementation skills
Ddrphy ip design knowledge
The role involves developing logic design and RTL coding for DDRPHY IP while defining architecture and microarchitecture features

Job Summary

  • The role involves developing logic design and RTL coding for DDRPHY IP while defining architecture and microarchitecture features.
  • Candidates must ensure design integrity by applying strategies to meet power, performance, area, and timing goals through rigorous quality checks.
  • The position requires collaboration with verification, timing, and physical teams to resolve technical issues and ensure successful IP handoff.

Matching Summary

The role involves developing logic design and RTL coding for DDRPHY IP while defining architecture and microarchitecture features.

Skills & Requirements

Must-have

  • 8+ years of RTL coding experience
  • SystemVerilog implementation skills
  • DDRPHY IP design knowledge
  • Power intent strategy definition
  • Static Timing Analysis support
  • Cross-domain signal handling

Nice-to-have

  • Knowledge of Synthesis and Auto P&R
  • Experience with post-silicon testing
  • Familiarity with Primetime tools
  • Strong communication with cross-site partners
  • Coaching and training team members

Key Requirements

  • 8+ years of RTL coding or IP integration experience
  • Experience with industry standard high speed bus protocols
  • Knowledge of analog circuits and mixed signal designs
  • Proficiency in Tcl/Tk/Perl/Python automation

Work Rights

Not specified

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