This role serves as the technical authority for defining the overarching Design for Test and Debug strategy for next-generation FPGA and SoC families
Job Summary
This role serves as the technical authority for defining the overarching Design for Test and Debug strategy for next-generation FPGA and SoC families.
The successful candidate will drive the adoption of advanced DFX features like IEEE 1687 and 3D-IC technologies to minimize test costs and accelerate time-to-market.
You will partner with global Silicon Architecture and Manufacturing teams to ensure DFT requirements are integrated into hardware specifications from the start.
Matching Summary
This role serves as the technical authority for defining the overarching Design for Test and Debug strategy for next-generation FPGA and SoC families.
Skills & Requirements
Must-have
10-12 years DFT/DFD experience
Hierarchical DFT and Scan Compression expertise
IEEE 1687 and IEEE 1838 standards knowledge
Multi-die chiplet architecture experience
Silicon bring-up and failure analysis skills
Tessent or Synopsys EDA tool proficiency
Nice-to-have
FPGA configuration RAM testing knowledge
ASIL-D functional safety standard experience
High-speed link testing (HSLT) background
Mentorship of senior engineering teams
Strategic stakeholder management capabilities
Key Requirements
BS/MS/PhD in Electrical/Electronics/Computer Engineering
Minimum 10-12 years hands-on DFT/DFD experience
At least 4 years in an architectural or lead capacity
Expertise in semiconductor end-to-end product life cycle