Engineer / Senior Engineer, Physical Design (asic Place & Route) (san Jose, Ca) (7429)
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San Jose, CA, US
Base: $110,000 to $160,000 py; bonus/equity: not s...
On-site
Rtl-to-gds physical implementation
Tsmc n16 or below technology
Block level floorplan analysis
As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff
Job Summary
As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff.
TSMC is the world’s leading dedicated semiconductor foundry with a strong reputation for manufacturing excellence and advancing semiconductor manufacturing innovations.
TSMC offers a competitive total compensation package including base salary, allowances, bonuses, comprehensive benefits, and extensive development opportunities.
Matching Summary
As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff.
Salary
Base: $110,000 to $160,000 per year; Bonus/Equity: Not specified; Benefits: Market competitive pay, allowances, bonuses, comprehensive benefits
Skills & Requirements
Must-have
RTL-to-GDS physical implementation
TSMC N16 or below technology
block level floorplan analysis
Perl/TCL language programming
timing closure ECO implementation
signal EM/Noise and Power IR/EM analysis
Nice-to-have
TSMC N5 and below technology
low-power implementation methodology
advanced timing signoff methodology
multi-million gate design tapeouts
hybrid work schedule
Key Requirements
Master’s degree in Electrical/Computer Science Engineering
3+ years of industry experience
experience with TSMC N16 or below technology
ability to work regularly at South Bay Area customer site
Work Rights
Ability to work regularly at South Bay Area customer site