Reliability Verification Technical Manager

Intel Corporation

Bangalore, India
Hybrid
Asic em/ir flow methodologies
Esd perc flow methodologies
Pdk development and quality assurance
Lead a team of engineers responsible for crafting, validating, and optimizing PDK collateral to support design teams across Intel's product lines

Job Summary

  • Lead a team of engineers responsible for crafting, validating, and optimizing PDK collateral to support design teams across Intel's product lines.
  • Drive innovation in tools, flows, and methods to optimize design functions such as circuit design, physical design, and verification.
  • Foster a productive work environment by setting clear goals, maintaining accountability, and supporting differentiated performance management.

Matching Summary

Lead a team of engineers responsible for crafting, validating, and optimizing PDK collateral to support design teams across Intel's product lines.

Skills & Requirements

Must-have

  • ASIC EM/IR Flow methodologies
  • ESD PERC flow methodologies
  • PDK development and quality assurance
  • EDA tools and PDK contents
  • Synopsys RHSC/Cadence Voltus
  • ICV/Calibre or Pegasus

Nice-to-have

  • Technology file developments
  • Tool certification process
  • Advanced IC manufacturing process nodes
  • Continuous improvement mindset
  • Cross-functional team collaboration

Key Requirements

  • 10+ years of industry experience with a Bachelor's degree
  • 8+ years of industry experience with a Master's degree
  • 5+ years of industry experience with a PhD
  • 2+ years of experience managing a team

Work Rights

Not specified

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