Soc Design Verification Engineer

Phizenix

Santa Clara, CA, United States
$160,000—$180,000 usd py
On-site
Uvm-based verification environments
Systemverilog assertions
C/c++ reference models integration
Develop, implement, and maintain UVM-based verification environments for SoC and IP-level designs

Job Summary

  • Develop, implement, and maintain UVM-based verification environments for SoC and IP-level designs.
  • Integrate C/C++ reference models within verification testbenches and ensure seamless co-simulation.
  • Collaborate with design, architecture, and validation teams to define verification plans, strategies, and coverage goals.

Matching Summary

Develop, implement, and maintain UVM-based verification environments for SoC and IP-level designs.

Salary

$160,000—$180,000 USD

Skills & Requirements

Must-have

  • UVM-based verification environments
  • SystemVerilog assertions
  • C/C++ reference models integration
  • IP and subsystem level debugging

Nice-to-have

  • Gate-Level Simulation exposure
  • Low Power Verification experience
  • ARM-based SoC architectures familiarity

Key Requirements

  • 10+ years of experience
  • Bachelor’s or Master’s degree
  • SystemVerilog proficiency
  • UVM methodology expertise
  • Assertion-based verification skills
  • C/C++ models integration experience
  • Debugging skills at IP and subsystem levels

Work Rights

Not specified

Tailored Resume

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